x86 segment descriptor cache behaviour?

Posted on Yesterday, 16:30

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by superfury

in PC Emulation

in PC Emulation

What happens when the limit of a byte granular expand-down segment (so the normal limit behaviour is inversed) is at or above FFFFh? Are offsets past FFFFh counted as valid (like when using a address-size override to use 32-bit offsets)? Or is anything counted as invalid in that case (it's basically …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on Yesterday, 16:19

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by superfury

in PC Emulation

in PC Emulation

Just improved two things on the x86 segment descriptor handling: - Make RSM properly set the CS segment descriptor mode to real or protected-mode/V86 mode on Pentium and up (applying the CS real mode limit behaviour on Pentium properly). - Make segment descriptor read/write/execute permission …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-16, 11:14

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by superfury

in PC Emulation

in PC Emulation

Modified immediate parameter reading faulting/aborting(including paging locks) to check for active instruction by checking the parameter passed to the immediate read function(indicating checking(0)/loading from instruction(1) or main fetching routine(3, for 286+ CPUs only)) instead of directly …

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Re: MartyPC

Posted on 2024-05-15, 19:01

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by superfury

in PC Emulation

in PC Emulation

How important is cycle-accurate emulation of a 286? By the time the 286 came around, most PCs were clones. You could target exact emulation of the 5170, but what programs would you be able to run that you couldn't before? The original PC and XT were the trailblazers, so when you're targeting them …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-11, 13:09

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by superfury

in PC Emulation

in PC Emulation

Hmmm.... Just discovered something weird trying to boot Windows NT 4.0 to verify CPU behviour to be working properly still. Somehow it reaches what seems to be opcode 84h (TEST r/m8,r8), but fails to fetch the modr/m parameters for some weird reason? Looking at the fetching precalcs, it looks like …

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Pentium Pro handling of VIP/VIF?

Posted on 2024-05-11, 02:15

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by superfury

in PC Emulation

in PC Emulation

I've been reading the "Pentium ® Pro Family Developer's Manual" Volume 3 a bit (I was checking out SMM stuff originally, to check for bugs), but eventually got a bit distracted and looked into VME, at Page "12-15": At table 12-2, it says: Method 3, VME 1, IOPL <3, Bit in Redir. bitmap X: General …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-11, 01:21

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by superfury

in PC Emulation

in PC Emulation

With those fixes, I now see the following at the error address: 00298:C00013BB is the location that still crashes. ESP is C13FBE98, with EBP being C13FBF70 FS points to selector 18F, which is located at 818012F4 (limit 33h, access rights F3h). DS is invalidated, all others (CS/SS/ES) being plain 4GB …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-11, 00:23

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by superfury

in PC Emulation

in PC Emulation

OK. Found some issues with the Pentium Pro save state map for SMM: - CR3 wasn't saved or restored. - FS and GS selectors weren't saved or restored. - On Pentium Pro and up, PDPTE weren't saved (though unused by the crashing operating systems, except Windows NT 4.0 perhaps). As they're undocumented …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-10, 13:30

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by superfury

in PC Emulation

in PC Emulation

Just rewrote ModR/M SIB disassembly to be formatted [displacement][+][base][+][index*scale], each component within brackets being optional and depending if the previous component is valid. So for example, it can result in: 12345678+ESP 78+ESP etc. The + is only added when the previous component is …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-07, 18:33

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by superfury

in PC Emulation

in PC Emulation

Looking at Windows 9x going wrong, I see something odd. It's faulting on a segmentation load that's out-of-range (in the GDT), but somehow I see it patching some odd variable in memory (looks for a write to [EDX] at the end of the procedure)? BIU T1 E 0028:c00013bb 8E 44 24 38 mov es,word ss:[esp++ …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-06, 02:19

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by superfury

in PC Emulation

in PC Emulation

And the latest bugfix on the 8042's output port (to ignore the bits 4-5 written on i4x0 devices to not trigger IRQs all the time) should fix the spurious 8042 IRQs with nothing buffered. Now Windows 95 changes behaviour once again, trying to load a GDT entry that's out of range this time instead ( …

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Re: 8042 output port bits 4/5?

Posted on 2024-05-06, 01:16

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by superfury

in PC Emulation

in PC Emulation

Although this issue is old, I noticed one odd thing with the latest CPU bugfixes. When the BIOS executes, I see it writing 0xDD and 0xDF to the output port for some odd reason, on the i440fx (don't know about other architectures yet)? It's probably enabling and disabling the A20 line, but also keeps …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-05-05, 22:03

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by superfury

in PC Emulation

in PC Emulation

OK. Just was interested and ran the test386.asm testsuite once again (Pentium II for all emulation support on the Compaq Deskpro 386 architecture). It ends up at POST 12h. So something is definitely wrong now, in the CPU emulation. The documentation of test386.asm says: Other memory access faults …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-28, 10:12

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by superfury

in PC Emulation

in PC Emulation

And did the same to handling. Trap flag also now gets ignored if it detects a SMI at the same time, giving priority and ignoring the trap flag handling.

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-28, 08:57

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by superfury

in PC Emulation

in PC Emulation

Moved both SMI and hardware interrupts(INTA to be exact) from (A)PIC (both use INTA timings right now) to be handled as special and instructions, instead of being fused into the first instruction after it. That simplifies handling both of them to be like normal instructions and improve searchability …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-27, 14:26

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by superfury

in PC Emulation

in PC Emulation

Just fixed an 'issue' where 80286+ GRP4/5 INC/DEC opcodes would check against read accesses first, then check against r/w accesses, instead of only checking against r/w accesses. This was introduced with the new handling of the GRP4 opcodes (and already invalidly present on GRP5 opcodes). That would …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-25, 10:08

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by superfury

in PC Emulation

in PC Emulation

Managed to fix one other bug exposed by SDL3 (SDL2 somehow doesn't seem to show the bug). There was an issue with multithreaded pointer registration and release that caused the memory allocations for disk write file structure allocations to fail, causing the disk write to fail, for example when an …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-24, 19:36

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by superfury

in PC Emulation

in PC Emulation

OK. With the latest interrupt bugfixes and other CPU improvements (things like improved B-bit handling and D-bit based protected mode handling from the source segment of interrupts, faults and far jump/call/ret and iret instructions) Windows 95 goes wrong during any boot it seems? It's trying to …

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-23, 11:29

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by superfury

in PC Emulation

in PC Emulation

Managed to fix an issue in the new SDL3 port of the common emulator framework. So now sound works properly again on SDL3. Also went and fixed some issues in sound device connection/disconnection on SDL2/3.

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Re: Testing and fixing UniPCemu's CPU and UniPCemu progress

Posted on 2024-04-22, 02:37

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by superfury

in PC Emulation

in PC Emulation

Just fixed a i82347 bug where the NMIMASK register was set to mask the wrong causes and could cause an NMI in various cases (due to swapping reset state of register C3h and C4h (register C4h set to 84h and C3h set to 00h). They're now properly set to 84h(for register C3h) and 3Eh(for register C4h). …

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